1. Technical Field
This invention pertains to the field of digital communications and computing systems, particularly to the field of self-configuring digital multiplexers and cross-connects.
2. Descriptions of the Related Art
Traditional digital multiplexer hardware logic relies on external, conventionally software based, systems and processes to configure which of the multiplexer input data elements to select for the multiplexer output on any given multiplexing timeslot (TS, i.e. multiplexing hardware clock cycle). The conventional, non-hardware automated multiplexing control processes however are not able to respond to needs to change the multiplexing input-to-output TS mapping configuration at the hardware signal clock rate.
Thus, the traditional multiplexers, when multiplexing input signals, for example from input ports #0, 1, 2 and 3, to a time-division-multiplexed output carrier signal carrying a repeating sequence of channel-TSs, for example TSs #0, 1, 2, . . . 11 repeated over and over (with an instance of the full range of output TSs, e.g. #0-11 in this example, referred to as a column), will select the same input # for any given output TS # column after column—unless and until the multiplexing input port to output TS mapping is reconfigured. As a specific example, assuming that the conventional multiplexer is configured (through its external control) to select the input #1 to its output TS #5, it will connect the signal from its input #1 on each of the TS #5 clock cycles in the repeating output carrier frame columns (comprising the channel TSs #{0, 1, 2, . . . 11}, {0, 1, 2, . . . 11}, {0, 1, 2, . . . 11} . . . ).
Changing the multiplexing mapping configuration using traditional techniques, which customarily involve multi-stage software processes (executing at a microprocessor and not at the multiplexing hardware) that are asynchronous to the multiplexing hardware clock rate, and which thus consume an imprecise but large number of multiplexing clock cycles, is not possible for each new multiplexing output TS. However, being able to change the input # that is connected for any given output channel TS # (e.g. changing the input port selection from input #1 to #3 for the considered output TS #5)—and being able to do similarly for each of the consecutive multiplexer output channel TSs #0-11, i.e., continuously at every consecutive multiplexing hardware clock cycle is necessary to achieve per-output-channel dynamic multiplexing, which would be needed for instance in order to maximize the multiplexed output carrier signal utilization efficiency in cases such as where data loads from the various input ports are time-variable, calling for adaptive multiplexing configuration.
Moreover, conventional multiplexing is limited to selecting data from a single input port for any given multiplexer output channel TS; e.g. in case of a byte-oriented input and output signals i.e. byte-wide multiplexing, traditional multiplexer will select the entire byte of data from a single input port for any given output byte TS #. Prior art multiplexers thus are not able to select bits of data from multiple source input ports to the same output byte TS. Traditional multiplexers thus have to keep their entire output (byte) TSs dedicated to a single input signal. However, for effective single multiplexing-TS accurate dynamic multiplexing control, it would be necessary (though not known to be possible based on prior art techniques) to be able select e.g. multiplexing signal control bits from different input ports to the same output byte TSs, and to do so dynamically based on the same clock cycle status of the input bits.
These factors create a need for innovation enabling individual bit timeslot granular, input status adaptive multiplexing hardware with single clock cycle dynamic operation.